Author: Tom Kerrigan
Date: 01:43:28 04/07/00
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On April 07, 2000 at 00:19:54, Robert Hyatt wrote: >I would parallelize the Hsu/Thompson design. Do a find-victim/find-aggressor >cycle for black and white in parallel. This is a one-cycle operation... with Really? It's been about 2 months since I last read about this stuff, but I thought it was a 2 cycle operation. First, assert find-victim, then latch some values, then assert find-aggressor. To do the white and black thing in parallel, I think you would basically need two move generators. Otherwise the attack signals would be all wrong. The FSMs are built with the assumption that the attack signals depend on the side-to-move. >things to hide the cost totally... Typical SEE cycle would take two to three >such cycles since most cases (at least last time I counted them) had only one You're ignoring my main point. Let's say that generating a move takes one cycle and doing SEE takes one cycle. Now let's say you're at a node where there are 5 captures and you get a cutoff after capture #2. If you rely on MVV/LVA, then you only have to spend 2 cycles generating moves. If you do SEE, then you have to generate all the captures (5 cycles) and do the SEE calculations for all of them (another 5 cycles). So doing SEE takes 10/2=5 times as long. This ignores the fact that the SEE is probably much more expensive than 1 cycle, and the added complexity/time of saving the list of captures/SEE values and then sorting them. I wouldn't be surprised at all if the SEE method took 10 to 20 times as long. >or two attackers for one side at most. It would not be easy... but it would >definitely be doable. I wouldn't want to try an FPGA design, probably, but >an ASIC? Hsu was looking for things to take up the last bit of real estate on >his ASICS. a SEE 'block' would be a useful addition (IMHO) He had to struggle to fit the Chiptest generator onto one ASIC. Admittedly, it was a 2 micron process, but that tells me that the logic might be more complicated than you might think. -Tom
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