Author: Robert Hyatt
Date: 16:58:30 06/03/98
Go up one level in this thread
On June 03, 1998 at 18:21:00, David Fotland wrote: >On June 03, 1998 at 17:28:35, Robert Hyatt wrote: > >>On June 03, 1998 at 14:44:19, Ernst A. Heinz wrote: >> > >>>>Compare this to a VLIW design. With VLIW you can scrap all of your >>>>scheduling logic and add execution units until your heart's content. >>> >>>The real problem of VLIW is that you shift ever more burdens of >>>squeezing >>>performance out of the processors into the compilers. This is of course >>>fine if you know how to do it -- but up to now most compiler >>>construction >>>experts doubt this is true for VLIW ... > >The compiler experts writing the IA64 compilers know how to make it go >fast. >You are correct that this is not easy, but HP has been working on this >problem since 1992, and has good compilers already. > >>> >>>=Ernst= >> >> >>And that's not as big a problem as the "next generation" VLIW machine. >>Which is, by definition, incompatible with the current generation, >>because >>you go from VLIW to VVLIW to get more performance, and now there is no >>compatibility... compare this to the X86 architecture that will run >>anything and act somewhat like a VLIW architecture without the >>incompatibility >>issue... > >This compatibility from generation to generation was a big problem for >the >first generation VLIW instruction sets (cydrome, multiflow, etc). It >has been >solved in IA64m which is part of why they like to call it EPIC rather >than >VLIW. Intel knows that backward compatibility is critical to their >success. >Look at the x86. They would not accept a new instruction set that had >compatibility problems going forward to new generations. And Merced >executes >x86 code, so it will still run anything you can run on your Pentium >today. > >> >>Anyone can build a pentium-compatible machine that grabs 4 instructions >>per >>clock rather than two or three as is done now. And it would not have to >>produce changes to the compiler or old compiled images... > >The problem is that if you want to issue 4 instructions in parallel they >have >to be independent. This is very hard on x86 because there are only 8 >registers. The fast 4 issue superscalar RISC all have 32 registers, and >EPIC has 128. The small register size really slows down x86, and it's >very >hard to change the number of registers without making a new instruction >set. > >David Fotland (one of the Merced/IA64/EPIC instruction set designers) or by taking a page out of the P6 design book and using "register renaming" although it obviously isn't the "perfect" solution. Problem is that the X86 architecture was brain-dead from the beginning, but it became the de-facto standard. Even in the 60's computers had at least 16 general purpose registers, or more. It was a dumb mistake that Intel has had to live with for 20 years... It's time for a revamp to get rid of that old architectural fiasco, and give us an architecture that is pleasant to program in assembly language, not one that makes you keep a supply of air-sickness bags handy... :)
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