Author: Eugene Nalimov
Date: 22:14:12 02/19/02
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Wrong. On the CPU I am currently working with: Integer division: ~40 clock cycles. L1/L2/L3 cache miss: ~150-200 clock cycles. 40 is of course less than 150, but I would not call it "negligible". Eugene On February 19, 2002 at 11:07:29, Gian-Carlo Pascutto wrote: >On February 19, 2002 at 10:48:25, Robert Hyatt wrote: > >>Many newer processors do >>the integer divide far slower than the AND I use now. > >OTOH, it is followed by an unpredictable random memory >access, which will make the division negligible on any >modern processor. > >-- >GCP
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