Author: Robert Hyatt
Date: 10:52:34 06/28/98
Go up one level in this thread
On June 28, 1998 at 13:34:36, Keith Ian Price wrote: >On June 27, 1998 at 15:48:19, Robert Hyatt wrote: > >>On June 27, 1998 at 15:32:50, Keith Ian Price wrote: >> >>>2^250= >>>1809251394333065553493296640760748560207343510400633813116524750123642650624 >>> >>>2^400= >>>2582249878086908589655919172003011874329705792829223512830659356540647622016841194629645353280137831435903171972747493376 >>> >>>The latter number is greater than the estimated number of atoms in the universe, >>>so making the gates may be troublesome. >>> >>>In case you were really interested. >>> >>>kp >> >> >>never thought otherwise. But sometimes it is difficult to explain simple >>concepts to Vincent without bringing out elementary math facts. He is of >>the opinion that to design a circuit you lay all gates out in a linear line, >>one gate per level, so that gate-delays == # of gates. I am *trying* to >>explain to him that this is *not* the way you design fast hardware. You >>lay things out horizontally whenever possible, to take advantage of the >>inherent parallelism in such hardware logic. >> >>so far, my lectures are going over his head... But I'll keep trying. >>But, as you notice, given 400 gate delays lets me put a *huge* amount >>of parallel stuff together... > >Yes, I saw that you were doing that, but in real terms, given 2.4 million >transistors on the chip (I think I recall that that is close), and with 1/3 of >the chip devoted to move generation and EGTB and tunable weight storage >(actually, it might be 2/3, but we'll stick with 1/3), and a conservative figure >of 3.2 transistors per gate (very conservative if you'll be latching a lot of >the values), this leaves 500000 gates. With 64 gates per bitboard for a simple >XOR, for example, it seems there must be a limit to the complexity of the >evaluation in the chip, given 8000 features in the evaluation. Since I don't do >hardware design, I realize my figures may be wrong, but if so can you please >explain. 8000 features * 64 bits = 512000 gates for a simple function, so does >that rule out the possibility that they are using bitboards? > > >kp I don't believe they do use bitmaps. If you look at the original Belle hardware description, ken had 64 "things" that looked like squares, but which were "smarter" than a smple mailbox. it was possible to ask, in one cycle, things like "who is the least valuable white piece attacking square X"... that was the basis for the MVV/LVA move ordering he used. So since DB is really "improved Belle on a single chip" I suspect that basic design was kept. Which means you ask "who has a white pawn" and get up to 8 bits set in a mask... and then use that... so that for pawns, you need only 1/8th the logic you were thinking of since you don't do the same thing for all 64 squares, just for the 8 (or less) squares holding white pawns... and once you get the terms computed there, it takes much less to let them interact with each other further up the "tree" in the hardware eval. IE compute a raw king safety (pawn shelter), the number of pieces directly attacking squares adjacent to the king, the number indirectly attacking these squares, how close other pieces are, and then combine those into a second order (or third-order or nth-order) result...
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