Author: Keith Evans
Date: 16:06:16 04/02/02
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On April 02, 2002 at 13:22:53, Slater Wold wrote: >Therefore, the only way to truly speedup Crafty, would be to make an FPGA >with a search and an eval. Which is a *much* harder task than a move > generator. Yes this appears to be more difficult and not as well described in the literature. The good news is that Marc Boule will publish his move generator design and that solves part of your problem. Maybe translating that from VHDL to Verilog could be a way for you to come up to speed in Verilog. I assume that you want to use Verilog based on a previous post. I personally prefer it, but won't get into that religious war here. If you stick with VHDL then you'll save the translation time... If you read Hsu's phd thesis he describes his Deep Thought evaluator which doesn't look too bad. I think that understanding all of the details of Marc's move generator will be a good start since some of the ideas are the same. I wouldn't try to design a Deep Blue style evalulator quite yet ;-) >PS Keith, do you have another e-mail address? Yahoo wouldn't accept e-mail from swbell.net because it's an open relay. :( I will send you another account which you can try. Regards, Keith
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