Computer Chess Club Archives


Search

Terms

Messages

Subject: Re: Memory benchmark comparison DDR333 vs RDRAM PC1066 !

Author: Robert Hyatt

Date: 19:45:32 12/02/02

Go up one level in this thread


On December 02, 2002 at 20:00:33, Matt Taylor wrote:

><snip>
>>I'm more interested in current hardware.  IE two 2.8ghz xeons with the E7500
>>chipset
>>vs the AMD 2600+/2700+ since they "seem" to be available...
>
>Wouldn't it be more accurate to test against another SMP system? A single 2.8
>GHz Xeon would contend with an AMD AthlonXP 2700, but using 2 would sway the
>odds just a bit I think. Actually, from what I have read and seen, the AthlonXP
>2700 can be expected to beat the 2.8 GHz P4 and exceed the 3.0 GHz P4 in some
>areas.
>

Sorry.  I was talking about head to head.  IE a single vs a single, or a
dual vs a dual.  No doubt a dual in either cpu would smoke a single in the
other...


>>I'll post the Intel numbers when the machine arrives, both with and without
>>hyper-threading.
>>But I believe that the hyper-threading stuff is what is going to make the 2xXeon
>>significantly
>>faster...  Since it seems to help for Crafty and Eugene has not fixed all of the
>>spin/loop problems.
>>I don't know if he fixed the Lock() asm stuff, but there is another place that
>>needs fixing to make
>>it really work efficiently.
><snip>
>
>Does hyper-threading really help that much? It seems like it would create more
>contention for limited resources (decoder, internal u-op cache, even some
>execution units). I would be extremely interested in seeing hyperthreading
>benchmarks with Crafty.


First, if you look at the concept of trace-cache, it is _behind_ the decoder,
and all it stores are decoded instructions (micro-ops).  Since Crafty uses the
_same_ code in all threads, it is likely that the shared L1 I-cache (and the
L1 D-cache and L2 cache) will all contain stuff that is useful across the two
threads...

Eugene already ran some and posted the results.  The raw NPS went up by a
factor of 1.3X.  I think more can be had but at a couple of critical places
where I have a "busy spin" I need to insert a "pause" asm instruction so that
the cpu will work on the thread doing useful work if there is a choice...



This page took 0.01 seconds to execute

Last modified: Thu, 15 Apr 21 08:11:13 -0700

Current Computer Chess Club Forums at Talkchess. This site by Sean Mintz.