Author: Dezhi Zhao
Date: 13:54:05 12/04/02
Go up one level in this thread
On December 04, 2002 at 11:03:09, Jeremiah Penery wrote: >On December 04, 2002 at 04:39:10, Gian-Carlo Pascutto wrote: > >>On December 03, 2002 at 16:14:57, Jeremiah Penery wrote: >> >>>BSF/BSR on a P3 are like 1-2 cycle operations. On Athlon, they're more than 10 >>>cycles, plus they block other execution resources. >> >>How about the P4? >> >>-- >>GCP > >I assumed P4 was the same as P3, but I never could find instruction timing data >for P4. No. These instructions on P4 are much slower than on P3. I could not find out the latency numbers of these micro code instructions in any Intel manuals. These numbers might be too ugly to be listed there:)
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