Author: Robert Hyatt
Date: 19:51:35 12/13/02
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On December 13, 2002 at 21:55:09, Matt Taylor wrote: ><snip> >>>the problem is you lose time to the ECC and registered features of the >>>memory you need for the dual. of course that's the case for all duals. >>>both K7 MP and Xeon suffer from that regrettably. >> >>That is not true. The duals do _not_ have to have ECC ram. And it doesn't >>appear to be >>any slower than non-ECC ram although I will be able to test that before long as >>we have >>some non-ECC machines coming in. > >Actually he is correct about the registered ram. The "registered" feature is >that it delays longer than unregistered ram. This is important for stability. It >doesn't affect bandwidth, but it does affect latency. > ><snip> >>>With some luck by the time they release a 3.06Ghz Xeon they have improved >>>the SMT another bit. >>> >>>Seems to me they working for years to get that SMT/HT slowly better working. >> >>Not "for years". It was announced as a coming thing a couple of years ago and >>several >>vendors have been discussing the idea. And they are going to increase the ratio >>of physical >>to logical cpus before long also... > >I don't think so. HT won't scale terribly well. I made another post about that, >and I won't reiterate what I said there. > >-Matt I don't see why the two of you make such sweeping generalizations. What is to prevent modifying the L1 cache to spit out 256 bits of data at once? There is nothing internally that can't be improved over time, and the idea of a 4-way hyper-threaded cpu should eventually be just as effective as four completely separate cpus, although the price should be substantially lower. There is _nothing_ inherently wrong with taking the process scheduler completely out of the O/S and dropping it into the CPU. It makes perfect sense as the operating system context-switching time is so long that we can't afford to block processes for memory accesses, and have to block only for things that take far longer like I/O operations. Inside the cpu this context switching time becomes nearly zero, and the gains are significant. It might take a while to get there, but you will see 16-way SMT one day. Just as surely as you will one day see 4 cpus on a single chip...
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