Author: Tony Werten
Date: 00:04:54 12/14/02
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On December 14, 2002 at 00:56:19, Robert Hyatt wrote: >On December 13, 2002 at 23:27:02, Robert Hyatt wrote: > >>On December 13, 2002 at 23:19:22, Eugene Nalimov wrote: >> >>>P4 cache line size is 128 for L2 cache, 64 for L1 cache. >> >>Right. But is not any cache line miss that requires memory going to have >>to read 128 bytes? If it isn't in L1, and it isn't in L2, it is going to >>fill the L2 line, 128 bytes. If it is not in L1 but is in L2, then the >>memory read isn't needed and the latency issue for memory (as discussed >>here) doesn't apply?? >> > > > >I went back to study the PIV a bit more and it appears my initial thought >was correct. Everything that exists in L1 cache is guaranteed to also exist >in L2. And PIV yes, on AMD no. Tony >And L2 sucks in data from memory and it is the only cache that talks >directly to memory. The 20+K L1 micro-op cache and the 8K L1 data cache >talk only to L2. (Intel says 12K micro-ops, which seems to translate into >roughly 21K bytes of micro-ops, just to make this compare with the older >PIII with 16K I and D cache (L1). PIII has more Dcache, but less Icache. > > >The only issue is that a couple of the linux guys once quoted the intel PIV >specs as saying 64 bytes/line for L2 as well as L1, which contradicts some- >thing I had read (I think) on the Intel web site. Perhaps this was tuned to >RDRAM but not done on DDR RAM. I will hedge on this until I find a clear >and precise answer, which I have not been able to do tonight, so far. >
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