Author: Keith Evans
Date: 15:20:41 04/09/03
Go up one level in this thread
On April 09, 2003 at 18:01:09, Robert Hyatt wrote: >On April 09, 2003 at 16:58:35, Tom Kerrigan wrote: > >>On April 09, 2003 at 12:14:37, Robert Hyatt wrote: >> >>>_IF_ it is verified. This is not easy. It means you have to run a program that >>>specifically >>>tests "edge conditions" by running sliding 1 patterns thru every instruction, to >>>see if there is >>>any unexpected cross-talk at higher frequencies, etc. >>> >>>Just because it runs some application correctly, does _not_ mean it will run >>>_all_ applications >>>correctly. >> >>Do you know what testing Intel/AMD does to determine rated clock frequency? >>Seems like you should be able to do that, or something similar, without too much >>effort. >> >>-Tom > > >I know what Intel used to do. In fact, most every hardware manufacturer has >such >tests for their products. IE disk drives manufacturers, SCSI controller >manufacturers, >etc. > >Hsu had to develop the same tools for deep blue and he found some interesting >problems in >DB2 chips, if you have read his book... Doing a static timing analysis and finding the worst paths would potentially help. You would want to exercise those paths for sure. Only the designers can do this of course... And/Or you could perform a fault grading analysis on your vectors and see what % of the design that you're exercising, and assume that a very high percentage of testing will catch problems. Most ASICs aren't speed binned, so I'm not sure how Intel/Amd handles this sort of thing. I know that Hsu had some interesting structures such as on-chip tristate busses which can make timing analysis difficult.
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