Author: Anthony Cozzie
Date: 15:18:05 04/11/03
Taken from: http://www.intel.com/technology/itj/2002/volume06issue01/art01_hyper/p06_execution_engine.htm "The out-of-order execution engine has several buffers to perform its re-ordering, tracing, and sequencing operations. The allocator logic takes uops from the uop queue and allocates many of the key machine buffers needed to execute each uop, including the 126 re-order buffer entries, 128 integer and 128 floating-point physical registers, 48 load and 24 store buffer entries. Some of these key buffers are partitioned such that each logical processor can use at most half the entries. Specifically, each logical processor can use up to a maximum of 63 re-order buffer entries, 24 load buffers, and 12 store buffer entries. If there are uops for both logical processors in the uop queue, the allocator will alternate selecting uops from the logical processors every clock cycle to assign resources. If a logical processor has used its limit of a needed resource, such as store buffer entries, the allocator will signal "stall" for that logical processor and continue to assign resources for the other logical processor. In addition, if the uop queue only contains uops for one logical processor, the allocator will try to assign resources for that logical processor every cycle to optimize allocation bandwidth, though the resource limits would still be enforced. *By limiting the maximum resource usage of key buffers, the machine helps enforce fairness and prevents deadlocks.*" (emphasis added). The Pentium IV has two different modes, St0 and St1. In St1 mode the resources of the processor are hardwired to 50% each (resources like the RAT, etc, not the FUs or cache). I think this makes it pretty clear that the PIV is going to execute SMT code as fairly as possible. Obviously nodes do not take the same amount of time - EGTB hits are time consuming, while hash table hits are quick, but the scheduler itself is going to be as fair as possible. anthony
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