Author: Vincent Diepeveen
Date: 11:11:52 06/30/03
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On June 30, 2003 at 11:32:09, Anthony Cozzie wrote: >On June 30, 2003 at 09:01:02, Vincent Diepeveen wrote: > >>On June 30, 2003 at 00:09:06, Anthony Cozzie wrote: >> >>>>That program is so outdated technical seen that it still more or less fits in >>>>the L1 cache, nowadays called trace cache. >>> >>>I think you might understand a trace cache, but that statement is seriously off. >>> A trace cache is not a synonym for a L1 cache. >> >>P4 doesn't have a L1 instruction cache instead it has a trace cache which >>doesn't hold instructions but decoded instructions instead (so they do not need >>to decode them before executing, in itself a genious idea). > >Thats not all a trace cache does, but the point is the statement "the L1 cache, >nowadays called trace cache" is simply incorrect. Trace caches don't cache >data, nor is the Athlon's L1 cache called a trace cache. I'm simply saying that >you need to be more precise with your terms. ..aqd the shoe of the emperor is not red but it is actually mongolian red. Main point is that because of the trace cache, the P4 sucks ass. new instructions that need to get decoded go with 1 instruction a clock. Now for the 'streaming software' that might be great, knowing also the P4 has just 1 SSE2 execution unit (against opteron 2 or so), so the whole processor is build around the idea to execute 1 instruction a clock. That's more kind of a risc idea with CISC technology :) the opteron on the other hand tries to achieve 3 instructions a clock and is coming pretty close to that! Well done job by AMD. Intel has forgotten those customers who have well written software and who *can* do more than 1 instruction a clock at OoO processors. Best regards, Vincent
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