Author: Anthony Cozzie
Date: 17:11:59 07/03/03
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On July 03, 2003 at 15:02:55, Joachim Rang wrote: >On July 03, 2003 at 12:27:20, Ernest Bonnem wrote: > >>Does anybody here know the (somewhat detailed) technical reason ? >>Chip architecture ? >> >>On the average, for chess programs, a P4 running at frequency F is equivalent to >>an Athlon at frequency F times 2/3. >>Actually, it seems that this 2/3 ratio is no longer as bad for hi-end P4 (3.06, >>3.0 GHz) or the Mobile Pentium : any confirmation and reason ? > >The main reason is, that Athlon and P3 have 9 instructions per cycle and P4 has >only 6. > >Hyperthreading and higher FSB may improve the newest P4s. > >regards Joachim Chance of an Athlon ever retiring 9 instructions in one clock cycle: 0.00000000000000000001%. The main reasons the Athlon gets more instructions per clock (IPC) are its larger L1 caches and its smaller branch misprediction penalty. The PIV was designed to do DSP :) Anthony
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