Author: Gerd Isenberg
Date: 04:02:01 07/09/03
Go up one level in this thread
Current Opterons use so called "DirectPath Double" decode type for most SSE/SSE2 128-bit instructions, internally they do two 64-byte macroops. But AMD already mentioned "Future" Processors with 128-bit "DirectPath" SSE/SSE2 instructions: (Software Optimization Guide for AMD Athlon™ 64 and AMD Opteron™, Chapter 9 Optimizing with SIMD Instructions). That's a boost to floating point and also SIMD integer algorithms like KoggeStone. But when will it be? Like Athlon, Bitscan (bsf, bsr) and Bittest (btx) instructions are still Vector path pipe-blockers (but of course 64-bit). Same for moving data between gp- and xmm- or mmx- registers. Still no popcount and instructions for "reverse" arithmetics (radd, rsub, rneg), where the overflow passes from high to low :-( Cheers, Gerd
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