Author: Robert Hyatt
Date: 17:48:05 07/17/03
Go up one level in this thread
On July 17, 2003 at 18:55:05, Vincent Diepeveen wrote: >On July 17, 2003 at 18:04:56, Keith Evans wrote: > >>On July 17, 2003 at 17:55:54, Vincent Diepeveen wrote: >> >>>On July 17, 2003 at 15:23:19, Keith Evans wrote: >>> >>>>It will be interesting to find out the discrepancy in the reported latencies. >>>> >>>>I remember years ago that DRAM had a tRC of 110 ns, so in theory you could do an >>>>endless stream of random reads and not see a latency worse than 110 ns at the >>>>hardware level. (Excluding the occasional increase due to refresh.) >>> >>>Are you talking about cray supercomputers or something? >>> >> >>Low end graphics chips - this is a concern when you're doing things like drawing >>vertical lines. > >Is there a chipset and other stuff between RAM and a chip there? There is a _lot_ of stuff between the RAM and the CPU. BUS interface chips on the memory controller. The memory controller itself. The PCI bus arbitration. PCI bus interface to the L2 cache. L2 cache controller. L1 cache controller. MMU. You name it. That's why memory latency is not in the 50ns range since DRAM can actually deliver data that fast. Latency builds up all along the critical path from the DRAM chip to the CPU register.
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