Computer Chess Club Archives


Search

Terms

Messages

Subject: Re: Another memory latency test - result

Author: Gerd Isenberg

Date: 15:08:35 07/18/03

Go up one level in this thread


On July 18, 2003 at 17:21:43, Dieter Buerssner wrote:

>On July 18, 2003 at 16:53:29, Gerd Isenberg wrote:
>
>>dblat: 220 -  vdlat: 208  !?
>
>Perhaps, a consequence of some issues you mentioned. But still rather
>comparable.
>
>>Sequential access times are much higher than your's, hmm.
>
>Only for small offsets. From 16 on (16 means 16 * sizeof(void *), so actually
>64) your numbers are much better.
>

Strange - the whole memory access is a mystery to me. Fuzzy LSBs, Hardware
prefetch, whatever...


>>C:\Source\dblat\Release>dblat 300000000
>                 ^^^^^^^
>Du gehörst also auch zu den Warmduschern, die alles aus der GUI heraus machen!
>:-)
>

A mollycoddle (Warmduscher), no i like it cool, may be a lazybones?
Yes i love these wizzards - a few seconds and the project is ready ;-)
A had ever problems with makefile syntax...

Cheers,
Gerd


>Cheers,
>Dieter



This page took 0 seconds to execute

Last modified: Thu, 15 Apr 21 08:11:13 -0700

Current Computer Chess Club Forums at Talkchess. This site by Sean Mintz.