Author: Robert Hyatt
Date: 10:32:08 11/12/03
Go up one level in this thread
On November 12, 2003 at 11:55:20, Gian-Carlo Pascutto wrote: >On November 11, 2003 at 23:42:45, Eugene Nalimov wrote: > >>My point is: it's possible that due to the fact that quad Opteron is NUMA -- >not SMP -- system, for SMP-only program performance on quad Opteron can be >>worse than on *real* quad SMP system, even when for one CPU Opteron >>performance is much better. Itanium was used only as an example of such >>system, I never recommended rewriting any program for it. > >I don't understand how. The NUMA part is RAM. Even worst case on the Opteron >RAM is faster than Xeon SMP. So how could it ever be worse? > >-- >GCP Answer: cache coherency is terribly expensive on the opteron. It is way less expensive on the SMP Intel (and older AMD) platforms. The cache controllers have to talk to each other. They now do it through a "layered" hiarchy rather than directly. That hurts, and it hurts _seriously_ if you aren't careful.
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