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Subject: Re: Intel four-way 2.8 Ghz system is just Amazing ! - Not hardly

Author: Robert Hyatt

Date: 12:27:09 11/12/03

Go up one level in this thread


On November 12, 2003 at 15:15:12, Brian Richardson wrote:

>On November 12, 2003 at 13:34:09, Robert Hyatt wrote:
>
>>On November 12, 2003 at 13:18:48, Matthew Hull wrote:
>>
>>>On November 12, 2003 at 12:18:22, Anthony Cozzie wrote:
>>>
>>>>On November 12, 2003 at 11:55:20, Gian-Carlo Pascutto wrote:
>>>>
>>>>>On November 11, 2003 at 23:42:45, Eugene Nalimov wrote:
>>>>>
>>>>>>My point is: it's possible that due to the fact that quad Opteron is NUMA -- >not SMP -- system, for SMP-only program performance on quad Opteron can be
>>>>>>worse than on *real* quad SMP system, even when for one CPU Opteron
>>>>>>performance is much better. Itanium was used only as an example of such
>>>>>>system, I never recommended rewriting any program for it.
>>>>>
>>>>>I don't understand how. The NUMA part is RAM. Even worst case on the Opteron
>>>>>RAM is faster than Xeon SMP. So how could it ever be worse?
>>>>>
>>>>>--
>>>>>GCP
>>>>
>>>>Aaron's argument is: if a 1x opteron is faster than a 1x Xeon, a 4x opteron will
>>>>be faster than a 4x Xeon.
>>>>
>>>>Nalimov is saying that Fritz may scale worse on the opteron due to NUMA issues.
>>>>In other words, this is comparing latency with 1x opteron and NUMA opteron
>>>>relative to 1x Xeon vs SMP Xeon.
>>>>
>>>>Off hand this seems logical to me . . .
>>>
>>>Perhaps Eugene can tell us if SMP crafty was slower on 2x opteron than Bob's 2x
>>>Xeon, before the NUMA mods were made?
>>>
>>>MH
>>
>>Yes.  It was _really_ bad on the opteron.  But then again it was also not
>>real good on my xeon.
>
>Might you have meant bad on Athlon, not Opteron?

No.  It was bad on athlon.  _really_ bad on opteron.  :)


>
>Even though the NPS scaled _perfectly_ on my older
>>quad xeons.  The PIV went to a longer cache line, which caused some coherency
>>overhead that hurt.  This has been addressed in the current code.  But the
>>problem was worse on the opteron due to the NUMA delays, compared to the
>>PIV xeons which simply have a longer cache line to aggravate the problem.
>>
>>
>>
>>
>>>
>>>>
>>>>anthony



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