Author: Sven Reichard
Date: 15:22:13 12/06/03
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On December 06, 2003 at 18:13:52, Sven Reichard wrote: >On December 06, 2003 at 18:11:02, Anthony Cozzie wrote: >>> >>The athlon's MMX ALUs are fully pipelined, meaning that they can retire 1 >>instruction/clock each. >> >>anthony > >So the 2 cycle latency stated in the Optimization Guide is incorrect? > >Sven. Or maybe I misunderstand the notion of latency... Anyway, thank for your prompt reply. Sven.
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