Author: Gerd Isenberg
Date: 14:05:03 01/16/04
Go up one level in this thread
>After looking a while to your source, i think your code is very similar to mine, >except the data density of your Indices and the identifiers ;-) > >// slide indices: >unsigned int SlideIndexH[8], // horizontal > SlideIndexV[8], // vertical > SlideIndexRU[16], // right up (RU) > SlideIndexRD[16]; // right down (RD) > >I use(d) something like this: > >// slide indices == rotated bitboards: >unsigned char SlideIndexH[8], // horizontal > SlideIndexV[8], // vertical > SlideIndexRU[8], // right up (RU) > SlideIndexRD[8]; // right down (RD) > >But with bitboard declaration instead of BYTE[8] (what about a union?). >The only trick is to pack the 15 diagonals byte aligned into eight bytes and >address them in this manner. > >rightupIdx = (sq-Rank(sq)) & 7; >rightDownIdx = (~sq-Rank(sq)) & 7; Bob's trick (with other mapping i guess) is to have all that state indices in precalculated arrays: (s>>3)+(s&7) == rightupIdx[s] 7-(s>>3)+(s&7) == rightDownIdx[s] His index is simply a bit index. The amount of how many bits the occupied board must be shifted right, to get the desired occupied state with final "and 63". Variable 64-bit shift right is a pain for x86-32, but with 64-bit cpus it may be faster: Bob has something like this: (SlideIndexRDBB >> rightUpShift[s]) & 63 1 very cache friendly memory read 1 64-bit shift right 1 and 2 (3)instructions, two register required. We have three or even four instructions, two registers needed for diagonals. Bob's approach, in opposite to mine (but not your's) has no possible "Store-to-Load Forwarding"- problem - to store 64-bit wise and to read "unaligned" Bytewise short after: Software Optimization Guide for AMD Athlon™ 64 and AMD Opteron™ Processors: Chapter 5 Cache and Memory Optimizations 5.4 Store-to-Load Forwarding Restrictions
This page took 0 seconds to execute
Last modified: Thu, 15 Apr 21 08:11:13 -0700
Current Computer Chess Club Forums at Talkchess. This site by Sean Mintz.