Author: Ernst A. Heinz
Date: 20:50:45 01/26/00
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>What on earth are you talking about? I never said anything about sending DB >40,000 instructions. I said Hsu might be thinking of the number of different >"things" he does in the chip... which doesn't necessarily mean that those >translate directly to x86 assembly instructions. IE when I (using bitmaps) >ask the question "is this pawn passed" I think of that as one operation, >because it _is_ using bitmaps. In Cray Blitz, it was _not_ one instruction >by a long shot... > >You have two different expertises trying to talk with a common language. I >would not assume that Hsu meant 40K x86 instructions. I would not assume >he meant 40K gates. I would not assume he meant 40K "things" on the chip that >get done for each node. In short, I wouldn't assume anything, I would ask. Hey you two fighting cocks ... :-) Let me quote from Hsu's IEEE Micro article again (page 72). "The chess chips provided enormous computational power. On a general-purpose computer, the computation done by the chess chip for a single chess position requires *** up to 40,000 general-purpose instructions ***. At 2 to 2.5 million chess positions/s, one chess chip operates at the equivalent of a 100-billion instruction/s supercomputer." Clear enough now? Hsu's estimate obviously reads: 1 chess chip ~= 40,000 general-purpose CPU instructions per node =Ernst=
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