Author: Robert Hyatt
Date: 19:32:29 03/03/00
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On March 03, 2000 at 11:02:14, Brian Richardson wrote: >On March 02, 2000 at 18:08:13, Robert Hyatt wrote: > >>On March 02, 2000 at 16:43:10, Brian Richardson wrote: >> >>>IBM's next-generation "Giga" processor (or Power4) due in 2001 will have 2-way >>>onchip SMP. Compaq has similar plans for Alpha. Intel not next 2-3 years as >>>far as I know. >> >> >>Didn't Ncube already do this? 4 per chip? > >No, to the best of my recollection (TTBOMC?), Ncube was always an MPP (massively >parallel) architecture, not SMP. Generic Intel processors, and lots of >them--funded by Oracle/Larry Ellision, but of course never worked as a general >purpose commercial server, since Oracle DBMS has strong architectural affinity >with the shared resources programming model. I think Ncube has since evolved to >target the video streaming market, where MPP is just fine. > >I don't think we have seen on-chip SMP yet, although I suppose the old VLIW >implementations were somewhat close, and certainly current superscalar >processors with the ability to execute several instructions in parallel are also >related, but not true SMP. None of the intel machines beyond 8-way have been SMP machines (to the best of my knowledge). Machines like the touchstone, et al, were all clusters of single-cpu machines using a message-passing interface. Not shared memory. I had thought that Ncube (another message-passing machine) used chips with 4 processors to build boards with 16 processors that they could plug into their message-passing backplane for large numbers of processors... But in any case, there are very few SMP machines with > 8 processors. Dec and Sun and SGI are the primary actors in this arena so far, and N is small (<= 32 so far).
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