Author: Eugene Nalimov
Date: 11:38:16 03/05/00
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On March 05, 2000 at 03:10:57, Tom Kerrigan wrote: >On March 04, 2000 at 23:17:45, Robert Hyatt wrote: > >>>In that case, I don't think it's possible to use Crafty to compare the processor >>>cores. The TSCP benchmarks give much more accurate data in that regard. >>> >>>-Tom >> >> >>Only for small programs. What about programs with larger cache footprints? > >I don't see why you want to bring the cache into this, if you just want to >compare the cores. (Which I do.) > >>Which means no register jams occur in the program. For more complex programs, >>the renaming logic in the P6 avoids many register jams/spills and does much >>better keeping both pipes filled. > >Do you have any proof of this? > >Here's a simplification of the issue, but it helps to illustrate the problem: > >The P5 has a 5 stage pipeline. For it to be full, it needs to be executing >2*5=10 instructions at once. The P6 has a 12 stage pipeline. It needs 12*2=24 >instructions to be full. > >So if somebody told me that the Pentium's pipes are usually more full than the >P6's pipes, I would have absolutely no problem believing it. Even if the P6 does >have all sorts of fancy features. > >-Tom You forget that P6/PII/PIII can run at much faster frequence - exactly because of a longer pipeline (and P5 is no exception here, please look at the PPC - it also have a very short pipeline, so it cannot run fast enough to remain competive with Intel). So when you are comparing them at the same frequence you are not doing the right thing. Eugene
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