Author: Eugene Nalimov
Date: 12:02:47 03/10/00
Go up one level in this thread
On March 10, 2000 at 14:30:43, Tom Kerrigan wrote: >On March 10, 2000 at 13:34:30, Eugene Nalimov wrote: > >>On March 10, 2000 at 03:21:31, Tom Kerrigan wrote: >> >>>On March 09, 2000 at 23:07:17, Robert Hyatt wrote: >>> >>>>that's the wrong way to measure this. the 8080 was a 16 bit cpu if you use >>>>that logic. The 68000 had a 16 bit bus. I taught hardware design courses at >>> >>>16 bit external data bus, yeah. But how wide were the register busses? How wide >>>was the ALU? I believe the answer to both questions is 32-bit. >> >> add.w d0, d1 - 4 clocks >> add.l d0, d1 - 6 clocks > >I'm not sure what this suggests. > >If the 68000 was purely 16-bit, it seems like add.l would take twice as long as >add.w. So maybe there's a 32-bit register bus that gets staged before the 16-bit >ALU, or something. Or the other way around, but that seems less likely. > >-Tom Other possibility is that there is some constant overhead per instruction - e.g. instruction decoding. Eugene
This page took 0 seconds to execute
Last modified: Thu, 15 Apr 21 08:11:13 -0700
Current Computer Chess Club Forums at Talkchess. This site by Sean Mintz.