Author: Laurence Chen
Date: 07:02:58 03/26/00
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On March 26, 2000 at 01:36:12, blass uri wrote: >On March 25, 2000 at 21:46:54, Laurence Chen wrote: > >>On March 25, 2000 at 21:21:55, Mogens Larsen wrote: >> >>>:o) >>Perhaps you can show me the math. A Celeron is a Pentium II modified chip >>running at 66 MHz Bus, and the Pentium III running at 667 MHz is a coppermine >>chip running at 100 MHz chip. Are you telling me that a dual Celeron running at >>66 MHz bus is faster than a Pentium III running at 100 MHz? Could you show me >>some benchmarks to prove it? The way I see it, it is like driving in a freeway, >>the Celeron got 6 lanes and the Pentium III has 10 lanes, and which freeway >>would get more congested? >>Laurence > >I do not understand what is the significance of this data (66 MH and 100MH chip >or 6 lanes and 10 lanes or pII modified chip and coppermine chip) for speed of >programs. > >Can someone explain exactly what does it mean for the speed of programs? >(I understood only from reading that big programs like tal do not like the >celeron but I do not understand the reason for it because I know almost nothing >about the structure of the computer). > >Uri http://www.anandtech.com/printarticle.html?i=1073 The following is a small extract from the link above: 256KB L2 The most noticeable difference between the Pentium III E and all previous Pentium III processors is that the Pentium III E features a full 256KB of on-die L2 cache operating at clock speed. This not only helps the platform scale better as clock speed increases but it also improves performance across the board. For those of you that aren’t familiar with the function of L2 cache, it is best summarized as a small amount of high speed memory. When storing data, the first place the CPU would like to have it stored would be on the chip itself, so that the CPU does not have to cross any slower busses to retrieve the data. The data can’t be stored just anywhere on the physical chip, it needs to be stored in some sort of memory location; this is cache. Let’s split the cache into two parts, the first, a small but extremely fast cache, and the second, a cache that’s larger but slower, but still faster than the system memory that the CPU would otherwise have to use to storeand retrieve its data from. Let’s call these two caches L1 and L2 respectively. The Pentium III processor (not the Pentium III E) features 32KB of L1 cache and 512KB of L2 cache. The L1 cache operates at the clock speed of the CPU (i.e. 500MHz) and the L2 cache operates at half the clock speed of the CPU. As you can see, 32KB is not a lot of space to store data, so only a very small amount of information can be stored in the Pentium III’s L1 cache. What doesn’t fit into its L1 can potentially go to the L2. While the L2 cache is obviously slower (in this case, 250MHz vs 500MHz) than the L1 cache, it is still faster than the system memory, which runs at anywhere from 66 – 133MHz depending on your system; in this case it would be running at 100MHz. The Celeron processor features 32KB of L1 cache and 128KB of L2 cache. In this case, both the L1 and L2 cache operate at the clock speed of the CPU (i.e. 500MHz). With these two processors, applications that can fit within the 128KB L2 cache of the Celeron will run faster on the Celeron 500 than they would on the Pentium III 500, because the L2 cache of the Celeron is running at twice the speed of the L2 cache of the Pentium III (500MHz vs 250MHz). At the same time, if you had an application that could not fit within the 128KB L2 of the Celeron but it could fit within the 512KB L2 of the Pentium III, then the application would run faster on the Pentium III because the Celeron would have to go all the way to the system memory in order to access the application. From a cost perspective, it is cheaper to integrate L2 cache onto the die (Celeron) than to mount the chips externally on a processor card (Pentium III). This is where the Pentium III E comes in. The Pentium III E takes the best of both worlds; it features half of the L2 cache of the Pentium III (512KB / 2 = 256KB) but they moved the L2 cache onto the die of the processor and thus it operates at the core clock speed of the processor.
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