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Subject: Re: Will the Itanium have a BSF or BSR instruction?

Author: J. Wesley Cleveland

Date: 11:02:55 08/18/00

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On August 17, 2000 at 14:28:28, Eugene Nalimov wrote:

>See "Itanium Processor Microarchitecture Reference", Order number 245473-001.
>Also available from Intel's web site for free.
>Main problem with your solution is intermix of integer (mov, and, shift by
>constant) and MMX (parallel add, shift by variable amount) operations.
>Int-to-MMX latency is 3 clock cycles. MMX-to-int latency is 4 clock cycles.
Even though I don't do MMX and integer operations on the same registers
(assuming that the result of czx is integer) ?

>On August 17, 2000 at 14:12:25, J. Wesley Cleveland wrote:
>>On August 16, 2000 at 13:11:04, Eugene Nalimov wrote:
>>>On August 15, 2000 at 23:27:46, Larry Griffiths wrote:
>>>>I looked through some literature for the Intel Itanium processor and did not see
>>>>any Bit Scan Forward or Bit Scan reverse instructions.  Does anyone know for
>>>>sure if the Itanium has these instructions or something like them.
>>>>My bitboard move generation would really suck without BSF or BSR.
>>>No. There are no such instructions. You have to use ifs, shifts, and lookup
>>>table. Here is the example -- FirstOne()/LastOne() that I wrote for IA-64
>>>version of Crafty (it is not in the official build yet):
>>I think you can do a lot better using the multimedia instructions (this is just
>>from reading the docs).
>>int FirstOne(BITBOARD arg1) {
>>  __asm {
>>  ld r1, arg1
>>  ld r2, 0fefefefefefefefeh ; probably is address of constant
>>  ld r3, 0101010101010101h
>>  padd1.uuu r4=r1,r2  ; each byte in r4 has fe if byte in arg1 was 0, else ff
>>  padd r4=r4,r3   ; now each non-zero byte in arg1 is zero
>>  czx1.l r2=r4    ; r2 has byte with first bit set or 8 if all 0
>>  shl r2=r2,3
>>  shr.u r1=r1,r2  ;first bit is now in low byte (or 0 if none set)
>>  and r1, 0ffh
>>  ld r0, btab[r1] ;not sure how to do this
>>  add r0=r0,r2

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