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Subject: Re: Why Shift after CZX Re: CZX IA-64 Instruction

Author: Brian Richardson

Date: 06:50:28 08/22/00

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I was thinking that a load instruction could load just the non-zero byte (base
address of the original 8 byte argument plus a register offset found by the CZX
instruction), and that the load would put that byte in the low order byte of the
register and zero fill the high order bits.  That would seem to combine several
steps (I may be thinking of other hardware architectures).  Then, just use that
as the offset into the pre-computed 8bits array.  There was a load single byte
form, but I'm not sure about the register offset and zero filling parts.

Alternatively, since IA-64 supports IA-32 instructions, what would the speed of
an "emulated" BSR/BSF look like on IA-64?  Of course, one would still have to
handle two 32bit portions as is done now, I think.

Thanks again for your patience and replys.

Brian Richardson

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