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Subject: Re: You got it backward, it is the chipset the cause of your problem !!!

Author: Vincent Diepeveen

Date: 15:01:35 01/20/01

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On January 20, 2001 at 09:17:12, Dan Andersson wrote:

>And RDRAM might be suboptimal for chess programs anyways (atleast until the next
>implementation anyways, Samsung I think)), so this might be a lose-lose
>situation.

For most programs it will slow down, but for DIEP i might be real
lucky with RDRAM single cpu that is as i get 8 probes of 16 bytes
out of RAM which is 128 bytes.

when running parallel of course RDRAM is a disaster. at 1.5Ghz
losing 150 clocks for a single lock is a bit much....

What i do not know is how much faster diep gets because of the
4 integers a clock the P4 can handle. All other things are not
favouring it like the small caches and the huge branch misprediction
penalty. It might get 25% faster but also 2 times slower, i don't know!

for sure newere releases of the P4 with 'bugfixed' architecture will
kick the butt of any P3 for my program.

Whatever speed they get however, the 100Mhz basic speed of the
rdram is going to be the slow factor in the end. 8kb L1 data cache
and 256kb l2 cache are not going to make up for the slow
latency of RDRAM



>Regards Dan Andersson



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