Author: Severi Salminen
Date: 08:54:36 02/15/01
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>For the Pro, PII and PIII and K7 this is no problem. Ok, thanks. It is a blessing for my movegenerator :) Now I'm able to extract the rank/file/diagonal state in just a couple of assembly instructions. >It is a BIG problem on the P4 however. How does it use SHR/SHL then? >But still the problem is not as bigtime a problem as a branch. >Eliminating possible mispredicted branches is crucial. > >the branch misprediction works initially quite simple. The first time >it sees the branch is considers fall through. > >If it goes wrong then it gives a penalty. For a short jump that's not >so big. If it is about a few tens of instructiosn the penalty already >gets bigger Well, this is a situation where my program decides which half of the 64-bit bitboard to use. They were very short jumps (2-3 instructions) but still the version without any jumps works faster - at least on Celeron300. Maybe even faster on these more branch-predicting processors (does Celeron use any logic on this?) Severi
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