Author: Gunnar Andersson
Date: 12:10:57 05/13/01
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A related issue: The AMD Thunderbird has two ports to the L1 data cache. The Pentium III has only one, and I think this is the case also for the Pentium IV (if I am wrong about this, please correct me). For my Othello program Zebra, the extra port to the L1 cache gives a speedup of 15-20% compared to a similarly clocked Pentium III. To achieve this speedup I had to rewrite the evaluation function in assembly; GCC introduced zillions of memory stalls in the original C code. It would not surprise me if chess programs exhibit the same behavior. In my humble opinion, cache performance is sometimes overlooked in the discussions on memory speed. / Gunnar
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