Author: Gian-Carlo Pascutto
Date: 07:49:20 05/24/01
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On May 24, 2001 at 09:11:16, Ed Panek wrote: >With the Pentium III Xeon’s shrink to >0.18-micron process the processor core >was able to house an on-die L2 cache of up to 2MB, tremendously >increasing the cache performance of the platform. > >12K micro-op trace cache – This special >cache replaces and improves upon the traditional L1 instruction cache. The >8-way set associative Execution Trace Cache caches micro-ops after they have >been decoded and they are also cached in >the predicted path of execution. This helps to hide some of the performance >penalties caused by such a long pipeline. > >256KB Advanced Transfer Cache – The >Xeon’s L2 cache subsystem is quite incredible to say the least. Not only does >the processor have a 256-bit internal pathway to its L2 cache, it is also able >to transfer data from the cache once every >clock meaning that it has the highest peak cache bandwidth figures of any >processor in its class. Hellooo? Is Intel still smoking crack or something? They are selling their new 'Xeon' with one EIGTH of the cache size of the old one. And that in a domain where it is _vital_(*) to the performance of the chip. Also, the trace cache is _still_ only 12K. Because their CPU can barely decode 1 instruction per clock it is a major performance stopper. Is there something wrong with their process technology that makes them unable to make bigger caches or what? (*) I seem to remember an SMP system must keep both caches synchronized, and hence the actually available cache is 1/n with n the number of processors. Or something like that. Maybe someone using SMP can comment? -- GCP
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