Author: Gian-Carlo Pascutto
Date: 02:53:25 01/10/02
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On January 10, 2002 at 05:07:37, Tom Kerrigan wrote: >It's the first x86 chip to have a trace cache. Hardly impressive, crippled as implemented, minor extensions of a known theme. >Its branch predictor is probably the best ever made >by anybody. Again, minor extension of a known theme. They also had no choice given the pipeline. >It's the first chip that I know of that has a double clocked ALU. Yes! This is the one thing I found very impressive. >It has SMT logic (although not enabled currently). Nothing new in that, and as you say, it's not even enabled. >How do you know that a "smarter" chip would outperform a faster clocked chip? I didn't think I said that (if I did, it was a typo). I just would _like_ that to be the case, because I find them more interesting. >Besides, how do you know it's even possible to make a smarter chip than the P3? Even Intel seems to think so given the Itanium. The first benchmarks weren't exactly encouraging though. I hope that improves with the next generations soon. -- GCP
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