Author: Tom Kerrigan
Date: 14:09:24 01/10/02
Go up one level in this thread
On January 10, 2002 at 05:53:25, Gian-Carlo Pascutto wrote: >On January 10, 2002 at 05:07:37, Tom Kerrigan wrote: >>It's the first x86 chip to have a trace cache. >Hardly impressive, crippled as implemented, minor extensions of >a known theme. What about the P4's trace cache is crippled? And what is it a minor extension of? Trace caches, AFAIK, have only been used in extremely obscure VLIW computers that existed more than a decade ago. >>Its branch predictor is probably the best ever made >>by anybody. >Again, minor extension of a known theme. They also had no >choice given the pipeline. If your job was to make branch predictors, I don't think you'd be saying that. You might as well say the entire P4 design is a minor extension of a known theme, the theme being microprocessors. >>It has SMT logic (although not enabled currently). >Nothing new in that, and as you say, it's not even enabled. How is that nothing new?? What other processors have SMT, besides that one super-obscure mainframe processor that isn't being made anymore and that I forgot the name of? >>Besides, how do you know it's even possible to make a smarter chip than the P3? >Even Intel seems to think so given the Itanium. The first benchmarks >weren't exactly encouraging though. I hope that improves with the next >generations soon. The Itanium doesn't get higher ILP from x86 code. Apples and oranges. -Tom
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