Author: Robert Hyatt
Date: 14:46:39 06/24/98
Go up one level in this thread
On June 24, 1998 at 16:50:10, Vincent Diepeveen wrote: > >On June 24, 1998 at 13:49:04, Robert Hyatt wrote: > >>On June 24, 1998 at 13:33:41, Keith Ian Price wrote: >> >>>On June 24, 1998 at 09:07:50, Ernst A. Heinz wrote: >>> >>>> Hot Chips 10 Advance Program >>>> >>>> August 16-18, 1998 >>>> Memorial Auditorium, Stanford University >>>> Palo Alto, California >>>> >>>>[...] >>>> >>>>2:30-4:00 Session 4:Specialized Chips Alan Smith ,chair >>>> >>>>Designing a Single Chip Chess Grandmaster While Knowing Nothing about Chess >>>> Feng-hsiung Hsu, IBM T. J. Watson Research Center >>>> >>>>[...] >>>> >>>>Any computer-chess enthusiasts from the US going there ... ? >>>> >>>>=Ernst= >>> >>> >>>I wonder if it will just be his standard 1.5 hour talk with a new title for the >>>theme of the symposium. I could get down there relatively easily, if I thought >>>he could say anything in depth in 1.5 hours. I would guess it is just the same >>>presentation, though. >>> >>>kp >> >> >> >>I'd suspect it is different, based on the conference. But it also might not >>have much of the data we'd like to see. IE I suspect that it will be less about >>chess, and more about how the hardware was designed to do certain time-critical >>functions efficiently, and how architectural problems were addressed over the >>evolution from chiptest to deep blue II. >> >>Would still be interesting to hear, but more from a hardware perspective, based >>on the "hot chips" title... > > > >Few newbie questions for Hsu, maybe someone can ask them or some of >them; first attempt to make a question list for Hsu: > > -how big is the hashtable on that processor, or didn't he implement it at > all at it? > Not sure... each group of chess processors has a shared hash, but each group can't see the hash from any other group. No way to do a 256-port shared memory... > -why doing a fixed depth at a processor, sounds very stupid to me they don't... they just do the *last* 4 plies of the search, plus the quiescence, in their hardware. This is dictated not by the speed of the chess processors by them selves, but how quickly the IBM SP2 front-end can feed them positions to search. If you reduce this depth to 3 plies, the chess processors outrun the SP2 processors and have to wait. If you increase the depth to 5 plies, the SP2 processors overrun the chess processors and they have to wait. It's a balancing act. > > -how fast is communications with his design with the mainframe/supercomputer hardware cycle time. *very* fast, just like shared memory. > > -how many cycles takes an evaluation at his hardware single chip? the chess processors can run at 24mhz, and search 2.4M nodes per second each. SO that factors into 10 clock cycles to do *everything* from generating moves, making moves, handling alpha/beta, doing the fast and slow hardware evals and so forth... all in 10 cycles. > > -what micron technology, 0.60? > -what megaherz speed runs CPU at? chess processors at 24mhz. Not sure about the SP2 they used, maybe 300mhz per processor. > > -how to design on CPU's knowledge depending things which depend on > other knowledge in a smart and lossless way speed it up? cannot parse the above.. :) > > -how many transistors on CPU (or does this sound cruel?)? I saw this number, but can't recall for the life of me. Enough that they actually put some 3 piece endgame databases right on the chip to finish filling it out... > > -how many dollars is pressing one CPU when pressing say 10,000? not super expensive, although I have not seen a price quote. They used project "MOSIS" for the fabrication work, and a silicon compiler to design the thing... That's all I recall... > >Greetings, >Vincent
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