Author: Tom Kerrigan
Date: 14:28:40 03/24/02
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On March 24, 2002 at 10:37:02, Vincent Diepeveen wrote: >complete nonsense. a single P4 can't even outgun a single cpu MP K7. What planet are you on? I didn't mention Athlons ONCE in my post. >dual MP K7 1.2Ghz for DIEP. With 3 instructions a clock, 12KB instruction >trace cache and 1024 words for L1 datacache, it is of course insane to >run another process on a P4 processor at the same time. >The whole SMT is interesting for the future, but complete nonsense for p4. >Just a marketing hype. For sure not a single P4 can ever profit from it. And I'm sure you have measurements to back up this assertion? >Note that 'thread' gets confused by process here too. Processes can >execute something, threads are all *forced* to do things indirect >using extra registers as indirection, so for me there is a clear >speeddifference already between the 2. Let's skip that difference The only difference between a thread and a process is the memory they use. Intel's SMT presents the chip as two unique processors anyway. >Whatever the 'idle' time on processor A, process A1 is simply executing >way way faster than A2. Also A2 is completely trashing the 1024 words >L1 data cache and small 12kb iop tracecache How do you know that the processes don't get equal CPU time, and that two chess threads would thrash the caches? >Also i have no idea what takes more system time of the processor for my >program, but i assume it is the decoding of integer instructions and >branches and most important the 3 instructions a clock limit. How do you know your ILP is being limited by EUs? The P4 averages less than one instruction per clock when running most programs, and you're saying your program is different by a factor of 3? -Tom
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