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Subject: Re: Hammer info. And som SMP musings.

Author: Robert Hyatt

Date: 18:45:19 03/24/02

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On March 24, 2002 at 17:13:53, Tom Kerrigan wrote:

>On March 24, 2002 at 00:02:50, Robert Hyatt wrote:
>
>>On March 23, 2002 at 16:09:55, Tom Kerrigan wrote:
>>
>>>On March 23, 2002 at 13:38:45, Dan Andersson wrote:
>>>
>>>>SMT is of little or no consequence to chess programs. It might even slow it
>>>>down. You don't think it automatically doubles the amount of functional units on
>>>>a given CPU, do you?
>>>
>>>You're completely missing the point. SMT was invented and implemented because
>>>most of a chip's functional units are idle at any given point in time--using
>>>them for another thread gives you free performance.
>>>
>>>I haven't seen any benchmarks yet, but a quad P4 Xeon will appear to software as
>>>an 8-way system and while it will probably not be as fast as a full-on 8-way
>>>system, it will be much faster than a 4-thread system.
>>>
>>>-Tom
>>
>>This is only true of _one_ of the two threads can run mainly out of cache.
>>The processor will have the other thread stalled waiting on memory reads or
>>writes.  If the second thread needs memory, it is over...  But if it can run
>>out of cache, it can fill in the gaps nicely...
>
>Do you have a reference for the P4 only switching threads on main memory
>accesses?
>
>-Tom


That was the explanation the Intel engineers used when they first announced
this.  They made the comparison to processes and I/O on a conventional CPU,
and took the analogy to nano-scale with threads within a CPU and memory blocks.

I don't know if they do anything _else_ personally, as I haven't particularly
been that interested since it isn't being used much yet...



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