Author: Keith Evans
Date: 09:38:02 03/29/02
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On March 29, 2002 at 09:56:38, Slater Wold wrote: >http://shop.barnesandnoble.com/booksearch/isbnInquiry.asp?userid=15CZSVVCRJ&mscssid=D7J34EGJ23AA9M6RSDCG3M90N0UP0JX0&isbn=0780348257 > >Is it worth $500!? > >I have never in my life heard of a 29 chapter book costing $500. > >Anyone have a copy they want to give to me? ;) Seems ridiculous to me. You might try asking on comp.lang.verilog If you just want to see some examples of synthesizable verilog RTL you can: Check out Celia's page - http://home.europa.com/~celiac/ver_eda.html Use google groups to search comp.lang.verilog Beg somebody to send you the OVI verilog spec in pdf format Go to http://www.synplicity.com/ and download Synplify and the manuals. You won't be able to run the tools, but you can read their chapter on Verilog and look at their accompanying verilog examples. If you want to read up on verification start here: http://janick.bergeron.com/guild/ http://www.qualis.com/cgi-bin/qualis/library.pl If you want to read about all the EDA dirt: http://deepchip.com I hope that helps. I'm not sure what you're trying to do. Regards, Keith
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