Author: Keith Evans
Date: 11:36:47 03/29/02
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On March 29, 2002 at 13:54:13, Slater Wold wrote: >On March 29, 2002 at 12:38:02, Keith Evans wrote: > >>On March 29, 2002 at 09:56:38, Slater Wold wrote: >> >BTW, I don't think Verilog is OT because it's a HDL. Which relates to Computer >Chess. Because that's what I plan on using it for. ;) > >What I plan to do: > >Get Crafty to use HW CPU's (FPGA's) to reach over 100M nps. > >And do it with > 5 FPGA's. > >The new Virtex FPGA's can do over 1M gates, so I am *thinking* I should be able >to get about 25M nps on one. Good luck. I have access to a lot of this sort of thing at work, but am lacking the motivation to adapt it to chess right now. (I hope that you can get access to EDA tools through work or something, because they are quite expensive.) We have a board with four XCV1000E parts that we used to prototype an ASIC at speed, and we're building a board with six of the XC2V4000 parts for a different architecture. One thing for you to consider is that a lot of the Verilog materials will assume that you're already a skilled digital hardware engineer. You absolutely need to know how to think like a hardware engineer before you'll be able to design and debug hardware - verilog doesn't change this. I think that parts of the coding will be quite tedious, so you might consider using scripts to generate verilog code for parts of your design. Lastly, before you start designing, you might want to propose your architecture here on CCC and get some feedback on whether or not the assumptions that you used in your performance calulations are valid. If your ideas are sound, then you might consider writing a proposal to Xilinx - they might be willing to assist you if they could use it as a part of a Deep Virtex marketing campaign. Mention that Altera is working on a Deep Apex/Stratix if they resist ;-) Regards, Keith
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