Author: Slater Wold
Date: 18:12:30 03/30/02
Go up one level in this thread
On March 30, 2002 at 18:45:40, Keith Evans wrote: >If you don't already have a copy of Hsu's thesis and IEEE micro articles, then >you should get copies of those. You won't find the Belle articles very >enlightening as they don't get into enough detail - just get copies of Hsu's >papers. Of course I do. ;) >Then when you're designing your move generator think about how an on-chip >microsequencer might want to interface to the move generator. And think about >how both would interface with some on-board evaluation hardware. Your PCI >interface could be a target only interface that's used to communicate to the >microsequencer. > >You'll probably find that using a ChipTest (move gen only) type approach just >slows Crafty down, but don't let that discourage you because you'll need a move >generator if you decide to make a more complete chess coprocessor later. IMHO >the next step for you would be to put a Deep Thought style design onto an FPGA >and maybe add transposition tables to that if your development board supports >external memory. Hsu never did glue on any transposition tables. Does anybody >know why not? Is there more to it than simply running out of time? I read an article where some college students made a FPGA based Chess Program, and they could not get a memory and/or TT to work. Also, where would you store the nodes from 200M nps x 3 minutes? >I think that if you start reading about all of the the features in final Deep >Blue chip then you might get a little overwhelmed. And it's a little mystifying >because some of the features are not well documented. I don't think that it >would be impossible to implement all of the features into one of the larger >Virtex parts, just keep in mind that Hsu spent a decade thinking about this >stuff so it will take a while. (You didn't propose doing this, but you might >eventually start thinking about it.) The chips in Deep Thought took 6 months to design and produce. The chips in Deeper Blue took > 3 years. This is just a start for me. Putting an eval and a search into a chip is *not* something I am interested in doing at this time, but KNOW I will seriously consider doing after my initial goals are met. There are FPGA's out there that could handle everything that a DB chip did, but uh, they are quite expensive. Perhaps when I get to that stage, they will have come down a bit, and it will be more feasible. >Regards, >Keith
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