Author: Tom Kerrigan
Date: 01:20:57 04/01/02
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On March 31, 2002 at 16:29:10, Keith Evans wrote: >generator for his program MBChess. His thesis is almost complete. Marc got his >program from about 2M nps to 10M nps using an FPGA for move ordering and movegen >only." > >Does he really say this? It sounds too good to be true. Let's take a look at >this from the perspective of the PCI bus. To be able to generate 10M moves per >second on a 33 MHz PCI bus, Marc seems to be implying that he can complete a PCI >read in 3.3 cycles and that the master will completely saturate the PCI bus with Right, and presumably much more data needs to be transferred than just reading moves. (I'd like to read the paper but I'm on dial-up right now.) Also, this assumes the logic can generate moves that fast. Seems like the critical paths for move generation would be pretty darn long on an FPGA; I'd be surprised if it could run at ~33MHz. (Not that it would necessarily have to, but I do think clock speed is a likely bottleneck.) Of course, my biggest problem with the 2M -> 10M NPS jump is that MBChess must be spending more than 80% of its CPU time generating and ordering moves, which is way beyond realistic, IMO. Interesting conversation, too bad I found out about it late. -Tom
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