Computer Chess Club Archives


Search

Terms

Messages

Subject: Re: A Response From Marc Boule

Author: Slater Wold

Date: 17:11:56 04/02/02

Go up one level in this thread


On April 02, 2002 at 19:06:16, Keith Evans wrote:

>On April 02, 2002 at 13:22:53, Slater Wold wrote:
>
>>Therefore, the only way to truly speedup Crafty, would be to make an FPGA
>>with a search and an eval.  Which is a *much* harder task than a move
>> generator.
>
>Yes this appears to be more difficult and not as well described in the
>literature. The good news is that Marc Boule will publish his move generator
>design and that solves part of your problem. Maybe translating that from
>VHDL to Verilog could be a way for you to come up to speed in Verilog.
>I assume that you want to use Verilog based on a previous post. I
>personally prefer it, but won't get into that religious war here. If you
>stick with VHDL then you'll save the translation time...

VHDL vs Verilog, I've read hundreds of articles trying to describe the "better"
points of them both.  When it comes down to it, well, I don't think it matters.

I will be using Verilog however.

>If you read Hsu's phd thesis he describes his Deep Thought evaluator which
>doesn't look too bad. I think that understanding all of the details of
>Marc's move generator will be a good start since some of the ideas are the
>same. I wouldn't try to design a Deep Blue style evalulator quite yet ;-)

Got'cha.  And got'cha.  ;)

>>PS Keith, do you have another e-mail address?  Yahoo wouldn't accept e-mail from swbell.net because it's an open relay.  :(
>
>I will send you another account which you can try.

Got it - Thanks!



This page took 0 seconds to execute

Last modified: Thu, 15 Apr 21 08:11:13 -0700

Current Computer Chess Club Forums at Talkchess. This site by Sean Mintz.