Author: Tom Kerrigan
Date: 00:20:53 04/03/02
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It's always flattering to see people working so hard with/from my code. :) I feel bad knocking people for doing something I haven't tried myself, but their hardware "design" was not good. It was basically a syntactic port from C to Verilog, with all of the loops intact. IMO, that's abusing the similarities between C and Verilog. You can't reasonably expect such a design to be much of an improvement over a software implementation (and their report indicates that it wasn't). Interesting to note that even implementing two small, non-memory-intensive parts of TSCP (a small program itself) was pushing the limits of their FPGA. Does anyone know how big that FPGA is relative to a Virtex or 4010? I assume a huge problem with space was that they were effectively synthesizing C code and probably did no floorplanning, but even so... -Tom
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