Author: Slater Wold
Date: 01:14:21 04/03/02
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On April 03, 2002 at 03:59:14, Tom Kerrigan wrote: >On April 03, 2002 at 03:43:10, Slater Wold wrote: > >>They have 15 weeks, and most of them are not very skilled in C. Remember, this >>is a HD class. Not a C class. But I agree, I think they should have added more >>flavor. > >All the more reason for them to be thinking in terms of "how do I detect attacks >with a grid of state machines" instead of "how do I implement a for loop in >Verilog," but oh well... Well, they'd have to read up on chess, and chess programming. Something I am sure none of them are interested in. Full course load at CMU + reading chess programming literature = F. :D BTW they do floorplan. Taken from one of the teams, "Unfortunately, Max + Plus II doesn't also provide a tool which can show you the logic visually. The floorplan editor attempts to give a visual representation of how the logic is mapped to LCELLS, but it is far from easy to understand, and not a great help when debugging your design." I got the feeling from several of the teams, the software they were given was not the easiest to use or understand. I will be using Synplify when I start my project, but based on what I've read about Max + Plus, I will steer clear of that program. > >>The class is Advanced Digital Design and basically it's a 15 week project, at >>CMU. From the class overview found at >>http://www.ece.cmu.edu/~ee545/f99/c/web/docs/proj.pdf: > >Jeez!!! I had no idea. Thanks for the link. How very flattering. :) > >-Tom YOU'RE FAMOUS TOM!
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