Author: Slater Wold
Date: 01:43:10 04/03/02
Go up one level in this thread
On April 03, 2002 at 03:52:25, Tom Kerrigan wrote: >On April 02, 2002 at 13:22:53, Slater Wold wrote: > >>I am going on vacation tomorrow for 2 weeks. When I get back I will profile >>Crafty, and then look into the possibility of porting the heaviest parts into HW >>generated via FPGA's. It is very possible that I will stick with making the >>move generator first, and then move on to the harder parts. > >I don't understand the Crafty fetish. It's just the program I know the best (which doesn't say much). In the begining this was just going to be a move generator, but I am not convinced that is worth the effort. > >A hardware implementation of any part of Crafty _should_ be completely different >from its software implementation. As long as you're doing something completely >different, why try to maintain consistency with something arbitrary? After reading for the last 12 hours, I will more than likely take the Belle/DT route. Which is not bad. We never really got to see how those things performed. >Also, what kind of FPGA are you planning to use, that you're going to implement >an entire eval function? I ask because I believe it would be impossible to fit a >single set (6) of piece-square tables on the largest Virtex, not to mention >actual logic, although I do notice that the Virtex-II Pro has 22592 slices >(!!!). I also bet it costs more than my life's savings... I wasn't *planning* on using a very large one. But since I am going to be adding eval, then I will of course have to.
This page took 0 seconds to execute
Last modified: Thu, 15 Apr 21 08:11:13 -0700
Current Computer Chess Club Forums at Talkchess. This site by Sean Mintz.