Author: Keith Evans
Date: 13:37:25 04/03/02
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On April 03, 2002 at 15:52:43, Robert Hyatt wrote: >On April 03, 2002 at 13:23:57, Keith Evans wrote: > >I hope I didn't say much about chiptest, because it didn't last very long. >But deep thought was definitely "belle on a chip" according to the write-up >by Hsu in the book "Computers, chess and cognition". Farther into the article, >Hsu says "the main difference between the processors is the enhanced hardware >evaluation function." (where 'the processors' is referring to the chiptest >machine vs the deep thought chip.) > I don't believe that I have a copy of "Computers, chess and cognition" but I do have a copy of Hsu's PhD thesis (F.-h. Hsu, Large-Scale Parallelization of Alpha-Beta Search: An Algorithmic and Architectural Study, PhD thesis, Carnegie Mellon Univ., Computer Science Dept., Feb. 1990) which contradicts this. I don't have it in front of me right now, but it is quite clear that the only custom silicon in Deep Thought is the single chip move generator. The only other arguably custom chips are Xilinx LCA's which are used to implement the evaluation logic. The slow evaluation really just looks at pawn structure and how rooks control files. Based on what I read about Belle it was more extensive than this, but perhaps more limited in it's searching algorithms. Hsu expresses some amazement at how well his relatively simple evaluation performed in competition. >No idea about the above usage of FPGA. Ken used that acronym in a paper he >wrote prior to 1984... My guess would be that he referred to FPLAs, but it doesn't really matter. Whatever they used was quite simple compared to what is available today, and they had to do a lot of board level and system level design as a result. Do you know how much time they spent designing, building, and debugging Belle? Seems like at least a year long full-time project for the average engineer - especially if you include all of the different versions. Regards, Keith
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