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Subject: Re: HW based Crafty (Boule's thesis)

Author: Robert Hyatt

Date: 14:49:58 04/03/02

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On April 03, 2002 at 15:41:31, Tom Kerrigan wrote:

>On April 03, 2002 at 11:44:45, Robert Hyatt wrote:
>
>>Again this depends on the FPGA you are looking at.  DB processors ran at
>>20-24mhz, and searched at 2M-2.4M nodes per second each.  Hsu later reported
>>that at least a factor of 15 speed-up would be possible with newer fab
>>processes.  He predicted 36M for .18u as a first guess...
>
>Uhhhh, are you clear on what an FPGA is? DB had absolutely nothing to do with
>FPGAs in any way, shape, or form. You're comparing a motorcycle to a paddle
>boat, and I'm not even sure what conclusions you're trying to draw from that
>comparison.


Yes I am aware of what an FPGA is.  I believe that a SOTA (state of the art)
fpga can run just as fast as the 3 micron (three micron, not .3) micron process
ASICS used in the original DB hardware...  3 micron ASICS in DB only ran at
24mhz.  An FPGA can certainly be run at that clock speed...




>
>>They've been around forever in various forms.  Look up Ken's paper on
>>Belle.  Or his paper "An FPGA based move generator for the game of Chess"
>>or any of several other publications including the second edition of
>>"Chess skill in man and machine."
>>
>>Belle used them in 1980, for certain.  I don't know how long they had been
>>out by then...
>
>The way I remember it, Belle was a mess of PALs and TTLs. If you just meant that
>Belle used programmable logic, then yeah, I'll buy that. PALs have been around
>forever.
>
>-Tom


I'm only quoting from the title of a paper Ken wrote, which was "An FPGA chess
move generator" or something to that effect (I quoted the exact title elsewhere
in this thread...)  I think you can locate a reference to it by searching for
"Belle chess machine" on Google...




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