Author: Keith Evans
Date: 16:15:20 04/03/02
Go up one level in this thread
On April 03, 2002 at 17:49:58, Robert Hyatt wrote:
>On April 03, 2002 at 15:41:31, Tom Kerrigan wrote:
>
>>On April 03, 2002 at 11:44:45, Robert Hyatt wrote:
>>
>>>Again this depends on the FPGA you are looking at. DB processors ran at
>>>20-24mhz, and searched at 2M-2.4M nodes per second each. Hsu later reported
>>>that at least a factor of 15 speed-up would be possible with newer fab
>>>processes. He predicted 36M for .18u as a first guess...
>>
>>Uhhhh, are you clear on what an FPGA is? DB had absolutely nothing to do with
>>FPGAs in any way, shape, or form. You're comparing a motorcycle to a paddle
>>boat, and I'm not even sure what conclusions you're trying to draw from that
>>comparison.
>
>
>Yes I am aware of what an FPGA is. I believe that a SOTA (state of the art)
>fpga can run just as fast as the 3 micron (three micron, not .3) micron process
>ASICS used in the original DB hardware... 3 micron ASICS in DB only ran at
>24mhz. An FPGA can certainly be run at that clock speed...
>
Actually.....
From the IEEE micro article:
"The chess chips in 0.6-micron CMOS searched 2 to 2.5 million chess positions
per second per chip." Capable of a 40 ns cycle time at best.
So we're comparing:
a full custom 0.6-micron, three-metal layer 5-V CMOS chip
^^^^^^^^^^ ^^^^^^^^^^^^^^^^^
with
an FPGA built using a 0.15 µm 8-Layer Metal process with 0.12 µm
^^^^^^^ ^^^^^^^^^^^^^
high-speed transistors.
It's somewhat design dependent, but in general I would feel fairly comfortable
saying that the FPGA should fare well. We prototyped an ASIC in Virtex parts
which are clocked at 80 MHz - it's not just a DMA engine but contains pieces
like 66 input multioperand adders. Something like a DMA engine design can easily
be clocked at over 100 MHz.
What does all this mean? We'll see. There may be design requirements which don't
map well to the Virtex architecture. For instance building a CAM for repetition
detection might be a bit tricky. Marc Boule was able to get his move generator
working at 33 MHz - so there's one datapoint. The move generator should not be
the bottleneck.
Regards,
Keith
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