Author: Keith Evans
Date: 21:29:45 04/03/02
Go up one level in this thread
On April 03, 2002 at 22:31:21, Robert Hyatt wrote: >On April 03, 2002 at 19:15:20, Keith Evans wrote: > >>On April 03, 2002 at 17:49:58, Robert Hyatt wrote: >> >>>Yes I am aware of what an FPGA is. I believe that a SOTA (state of the art) >>>fpga can run just as fast as the 3 micron (three micron, not .3) micron process >>>ASICS used in the original DB hardware... 3 micron ASICS in DB only ran at >>>24mhz. An FPGA can certainly be run at that clock speed... >>> >> >>Actually..... >> >>From the IEEE micro article: >> >>"The chess chips in 0.6-micron CMOS searched 2 to 2.5 million chess positions >>per second per chip." Capable of a 40 ns cycle time at best. >> >>So we're comparing: >> >> a full custom 0.6-micron, three-metal layer 5-V CMOS chip >> ^^^^^^^^^^ ^^^^^^^^^^^^^^^^^ >> with > > > >Aren't you switching to _deep blue 2_ now? I think I have something somewhere >that says that either the deep thought or deep blue 1 hardware was 3 micron, >I'll look it up when I hit the office. I think the IEE article was about DB2 >but again, I am not certain without having the article in my hand here at >home... > Oops. When I read what you wrote I read 0.3 micron - even after you spelled it out. (Hsu had mad some performance predictions for 0.35 micron in the IEEE article and the next to last chip that I worked on was 0.35 micron.) You are correct that Hsu's original move generator used a 3 micron MOSIS CMOS process. I should mention that the cycles times are also much slower than 40 ns. "The measured minimum cycle time is around 120-150 ns for FIND-VICTIM and FIND-AGGRESSOR cycles." So this is roughly a third the speed of Hsu's later chips. And Marc's FPGA design compares quite favorably with these numbers. Are you sure that the original Deep Blue used the 3 micron chip? I thought that there was a new generation of chips for that? >> an FPGA built using a 0.15 µm 8-Layer Metal process with 0.12 µm >> ^^^^^^^ ^^^^^^^^^^^^^ >> high-speed transistors. >> >>It's somewhat design dependent, but in general I would feel fairly comfortable >>saying that the FPGA should fare well. We prototyped an ASIC in Virtex parts >>which are clocked at 80 MHz - it's not just a DMA engine but contains pieces >>like 66 input multioperand adders. Something like a DMA engine design can easily >>be clocked at over 100 MHz. >> >>What does all this mean? We'll see. There may be design requirements which don't >>map well to the Virtex architecture. For instance building a CAM for repetition >>detection might be a bit tricky. Marc Boule was able to get his move generator >>working at 33 MHz - so there's one datapoint. The move generator should not be >>the bottleneck. >> >>Regards, >>Keith > > >The big headache is the same one present in DB. You can build a "search engine" >but you can't get much back from it other than "best move" and "score". I >really want the PV for testing/debugging. :) I have no idea how Hsu ever debugged his chips. (Both in simulation and in the lab.) He never wrote about having a software only version of his chess chips. Then when you throw in the parallel search - this is much more mystifying than anything that I've ever had to verify. >And then there is the hashing issue. Hsu included hash table support in the >DB 2 chips, but didn't have time to design/build the multi-port memory to get >the on-chip hashing functional. However, 80mhz sounds promising considering >DB used 10 cycles per _node_ for the search. That translates into 8M nodes per >second. Put a group of those together and this thing could fly... So he was planning on sharing the hash tables between multiple chess chips? I wish that he had published a data sheet for his chips ;-) Regards, Keith
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