Author: Tom Kerrigan
Date: 01:07:42 04/04/02
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On April 03, 2002 at 17:49:58, Robert Hyatt wrote: >Yes I am aware of what an FPGA is. I believe that a SOTA (state of the art) >fpga can run just as fast as the 3 micron (three micron, not .3) micron process >ASICS used in the original DB hardware... 3 micron ASICS in DB only ran at >24mhz. An FPGA can certainly be run at that clock speed... The information I found on the web indicates that Chiptest, not DB, was done with 3 um features. And that the DB or DB2 chips had 0.6 um features. (There is some ambiguitiy.) It makes sense that the DB and DB2 chips have the same feature size, though. They ran at pretty much the same clock speed, and I don't remember reading about FHH doing a shrink. I know that simple, pipelined, carefully floorplanned, general-purpose CPU designs run at ~100MHz on modern FPGAs. From what I know of the Belle/Chiptest/DT/DB move generator, I'd expect its critical paths to be at least twice as long, and probably longer. So I'd put an optimistic upper bound of 50MHz on it. And that's just the move generator; I'd expect the eval logic to be slower. But if you take the optimistic 50MHz number and the very overly optimistic 2-cycle-per-node number, you get 25M NPS, not "30M NPS easily." >I'm only quoting from the title of a paper Ken wrote, which was "An FPGA chess >move generator" or something to that effect (I quoted the exact title elsewhere >in this thread...) I think you can locate a reference to it by searching for >"Belle chess machine" on Google... The only paper I can find that's remotely similar to what you're talking about is Marc Boule's paper, from June, 2001. Even if Ken wrote a paper with that title, it doesn't mean the paper was written about something that was done in Belle. -Tom
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