Author: Keith Evans
Date: 09:48:11 04/04/02
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On April 04, 2002 at 04:10:52, Tom Kerrigan wrote: >On April 03, 2002 at 13:01:07, Keith Evans wrote: > >>Correct me if I'm wrong but I don't think that the piece square tables will be a >>problem. Let's take a pretty middle of the road part such as the XCV1000E - it's >>a basic Virtex FPGA without extended memory. There are 96 Block SelectRAMs in >>this part. You can configure them in different ways - I think that the most >>appropriate way for piece square tables is as 512x8. This is more than enough to >>hold 64*6 = 384 entries. And that's using 1 RAM - 95 are still available. > >Hmmm. I don't know about Block SelectRAMs. When I was using a Virtex for my >senior project, I used CLBs as 16-bit RAMs. > >-Tom Block SelectRAMs are quite nice. You can even configure them as dual port RAMs where the width of one side is different than the width of the other side. I think that Xilinx realized that they needed features like this to enable certain designs - probably the networking guys needed to build a lot of FIFOs. And the networking guys were able to afford to ship Virtex parts. Marc Boule considered using Block Select RAMs in his move generator to hold the Belle style disable mask stacks, but ended up using CLBs to reduce routing congestion. (Since they would have to be routed to each square.) After reading Marc's whitepaper, and rereading various Belle and Deep Thought/Blue papers I realized that Hsu keeps making a basic mistake when describing the Belle mask stacks. Hsu says that they are 2-bits wide, but they are actually just 1-bit wide. Marc is using roughly half of an XCV800 to implement his move generator plus a simple PCI interface. This doesn't leave much room for any sort of search/eval, so adding those would most likely require a larger FPGA. Regards, Keith
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